A typical analog phase-locked loop circuit includes a phase detector which determines the phase relationship between a reference signal and an output of the phase-locked loop, a charge pump responsive to the phase detector for setting a current or voltage representative of the phase relationship, a low pass filter which has a single cutoff frequency and is responsive to the current or voltage from the charge pump, and a voltage controlled oscillator which generates the output signal from the phase-locked loop circuit and which varies the frequency of the output signal in response to a control voltage from the low pass filter. A voltage regulator may optionally be present in order to provide a regulated supply voltage to the voltage controlled oscillator.
Existing voltage controlled oscillators for analog phase-locked loops have a single control voltage input that varies the frequency of the voltage controlled oscillator. If a wide frequency range is desired, then the voltage controlled oscillator is designed so that the single input has a large gain, expressed in Hertz/volt. However, the larger the gain, the more the jitter induced in the analog phase-locked loop as the charge pump increases and decreases the voltage on the loop filter capacitor.
Stability and minimal jitter require a relatively low gain, and the typical analog phase-locked loop circuit has a relatively low gain across only a limited frequency range. Thus, a problem with such a typical analog phase-locked loop circuit is that it is capable of stable operation with minimal jitter across only a relatively small frequency range. The typical analog phase-locked loop circuit can be designed to achieve low gain or a wide frequency range, but not both.